Field of the Invention
The present invention relates to a phase difference estimation device that obtains a phase difference between a synchronization code included in input communication data and a processing clock and a communication device having the phase difference estimation device.
Related Art
In the past, a method of synchronizing a master device and a slave device has been proposed. However, there is a phase difference between communication data that a slave device receives from a master device and a processing clock of the slave device, and this phase difference is a synchronization error between the master device and the slave device. As a technique for cancelling the synchronization error between the master device and the slave device due to the phase difference, a system that performs time synchronization between communication devices, for example, is disclosed in Patent Document 1. Specifically, this system transmits communication data for time synchronization from a master device to a slave device via a communication line. The slave device measures a phase difference between the phase of communication data and the phase of a clock signal of a destination clock domain by clock data recovery (CDR) when the communication data for time synchronization passes through a clock domain boundary in the slave device. By doing so, the slave device can correct the time of the slave device using the measured phase difference.
As a technique related to the present invention, a time measurement circuit is disclosed in Patent Document 2. Specifically, two oscillators 10 and 20 generate clock signals CLK1 and CLK2 having a cycle difference ΔT and a transmission pulse SP is output according to the clock signal CLK1. A reflection wave corresponding to the transmission pulse SP is received, and a reception pulse RP is output. A phase comparator 30 compares the phases of the clock signals CLK1 and CLK2 and outputs an in-phase signal P1, and a phase comparator 40 compares the phases of the reception pulse RP and the clock signal CLK2 and outputs an in-phase signal P2. A counter circuit 50 counts the clock signal CLK1 in a period where the in-phase signal P2 is output after the in-phase signal PI is output and measures a time difference τ between the transmission pulse SP and the reception pulse RP on the basis of a cycle difference ΔT between the count value N and the clock signals CLK1 and CLK2.
Patent Document 1: Japanese Unexamined Patent Application, Publication No. 2016-119548
Patent Document 2: Japanese Unexamined Patent Application, Publication No. 2002-196087